stm32f303xc::exti

Static EXTI_EVENTS

Source 
#[no_mangle]
pub static mut EXTI_EVENTS: u32
Expand description

The EXTI_PR (pending) register when set, generates a level-triggered interrupt on the NVIC.

This means, that its the responsibility of the IRQ handler to clear the interrupt source (pending bit), in order to prevent multiple interrupts from occurring.

EXTI_EVENTS is modeled to capture information from EXTI_PR register. In the top half IRQ handler, prior to clearing the pending bit, we set the corresponding bit in EXTI_EVENTS. Once the bit is set, in EXTI_EVENTS, we clear the pending bit and exit the ISR.

  1. Section 10.2.2, EXTI block diagram, page 243 of reference manual. ↩