Struct Port

pub struct Port<'a> { /* private fields */ }

GPIO port that manages 32 pins.

The SAM4L divides GPIOs into ports that each manage a group of 32 individual pins. There are up to three ports, depending particular chip (see¹).

In general, the kernel and applications should care about individual GPIOPins. However, mirroring the hardware grouping in Rust is useful, internally, for correctly handling and dispatching interrupts.

The port itself is a set of 32-bit memory-mapped I/O registers. Each register has a bit for each pin in the port. Pins are, thus, named by their port and offset bit in each register that controls is. For example, the first port has pins called “PA00” thru “PA31”.

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1. SAM4L datasheet section 23.8 (page 573): “Module Configuration” for GPIO ↩

Implementations

impl Port<'_>

pub const fn new_port_a() -> Self

pub const fn new_port_b() -> Self

pub const fn new_port_c() -> Self

pub fn handle_interrupt(&self)

Trait Implementations

impl<'a> Index<usize> for Port<'a>

type Output = GPIOPin<'a>

The returned type after indexing.

fn index(&self, index: usize) -> &GPIOPin<'a>

Performs the indexing (container[index]) operation.

impl<'a> IndexMut<usize> for Port<'a>

fn index_mut(&mut self, index: usize) -> &mut GPIOPin<'a>

Performs the mutable indexing (container[index]) operation.