Crate litex_arty 

Board file for a LiteX-built VexRiscv-based SoC synthesized for a Digilent Arty-A7 FPGA board

Modules

io 🔒

litex_generated_constants 🔒

Structs

LiteXArty 🔒

A structure representing this platform that holds references to all capsules for this platform.

LiteXArtyInterruptablePeripherals 🔒

Structure for dynamic interrupt mapping, depending on the SoC configuration

Constants

FAULT_RESPONSE 🔒

NUM_PROCS 🔒

Statics

PANIC_RESOURCES 🔒

Resources for when a board panics used by io.rs.

STACK_MEMORY 🔒

Size to allocate for the stack.

Functions

main^⚠

Main function called after RAM initialized.

start 🔒 ^⚠

This is in a separate, inline(never) function so that its stack frame is removed when this function returns. Otherwise, the stack space used for these static_inits is wasted.

Type Aliases

AlarmHw 🔒

ChipHw 🔒

ProcessPrinterInUse 🔒

SchedulerTimerHw 🔒