Module stm32f412g::clocks::pll

Main phase-locked loop (PLL) clock driver for the STM32F4xx family. ¹

Many boards of the STM32F4xx family provide several PLL clocks. However, all of them have a main PLL clock. This driver is designed for the main PLL clock. It will be simply referred as the PLL clock.

The PLL clock is composed of two outputs:

• the main one used for the system clock
• the PLL48CLK used for USB OTG FS, the random number generator and SDIO clocks

Implemented features

• Default configuration of 96MHz with reduced PLL jitter
• 1MHz frequency precision
• Support for 13-216MHz frequency range
• Support for PLL48CLK output

Missing features

• Precision higher than 1MHz
• Source selection
• Precise control over the PLL48CLK frequency

Usage

For the purposes of brevity, any error checking has been removed. In real applications, always check the return values of the Pll methods.

First, get a reference to the Pll struct:

let pll = &peripherals.stm32f4.clocks.pll;

Start the clock with a given frequency

pll.set_frequency_mhz(PllSource::HSI, HSI_FREQUENCY_MHZ, 100); // 100MHz
pll.enable();

Stop the clock

pll.disable();

Check whether the PLL clock is running or not

if pll.is_enabled() {
    // do something...
} else {
    // do something...
}

Check the clock frequency

let optional_pll_frequency = pll.get_frequency_mhz();
if let None = optional_pll_frequency {
    /* Clock stopped */
}
let pll_frequency = optional_pll_frequency.unwrap();
/* Computations based on the PLL frequency */

Reconfigure the clock once started

pll.disable(); // The PLL clock can't be configured while running
pll.set_frequency_mhz(PllSource::HSI, HSI_FREQUENCY_MHZ, 50); // 50MHz
pll.enable();

Configure the PLL clock so that PLL48CLK output is correctly calibrated

// The frequency of the PLL clock must be 1, 1.5, 2, 2.5, 3, 3.5 or 4 x 48MHz in order to get
// 48MHz output. Otherwise, the driver will attempt to get the closest frequency lower than 48MHz
pll.set_frequency_mhz(PllSource::HSI, HSI_FREQUENCY_MHZ, 72); // 72MHz = 48MHz * 1.5
pll.enable();

Check if the PLL48CLK output is calibrated.

if !pll.is_pll48_calibrated() {
    /* Handle the case when it is not calibrated */
}

Get the frequency of the PLL48CLK output

let optional_pll48_frequency = pll.get_frequency_mhz();
if let None = optional_pll48_frequency {
    /* Clock stopped */
}
let pll48_frequency = optional_pll48_frequency.unwrap();

---

1. See 6.2.3 in the documentation. ↩

Modules

• tests
  Tests for the PLL clock

Structs

• Pll
  Main PLL clock structure.