rp2350/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright OxidOS Automotive 2025.
4
5#![no_std]
6// GPIO has many register definitions in `register_structs()!`
7// and requires a deeper recursion limit than the default to fully expand.
8#![recursion_limit = "256"]
9
10pub mod chip;
11pub mod clocks;
12pub mod gpio;
13pub mod interrupts;
14pub mod resets;
15pub mod ticks;
16pub mod timer;
17pub mod uart;
18pub mod xosc;
19
20use cortexm33::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM33, CortexMVariant};
21
22extern "C" {
23    // _estack is not really a function, but it makes the types work
24    // You should never actually invoke it!!
25    fn _estack();
26}
27
28#[cfg_attr(
29    all(target_arch = "arm", target_os = "none"),
30    link_section = ".vectors"
31)]
32// used Ensures that the symbol is kept until the final binary
33#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
34pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
35    _estack,
36    initialize_ram_jump_to_main,
37    unhandled_interrupt,           // NMI
38    CortexM33::HARD_FAULT_HANDLER, // Hard Fault
39    unhandled_interrupt,           // MemManage
40    unhandled_interrupt,           // BusFault
41    unhandled_interrupt,           // UsageFault
42    unhandled_interrupt,           // SecureFault
43    unhandled_interrupt,
44    unhandled_interrupt,
45    unhandled_interrupt,
46    CortexM33::SVC_HANDLER, // SVC
47    unhandled_interrupt,    // DebugMon
48    unhandled_interrupt,
49    unhandled_interrupt,        // PendSV
50    CortexM33::SYSTICK_HANDLER, // SysTick
51];
52
53#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
54// used Ensures that the symbol is kept until the final binary
55#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
56pub static IRQS: [unsafe extern "C" fn(); 52] = [
57    CortexM33::GENERIC_ISR, // TIMER0 0 (0)
58    CortexM33::GENERIC_ISR, // TIMER0 1 (1)
59    CortexM33::GENERIC_ISR, // TIMER0 2 (2)
60    CortexM33::GENERIC_ISR, // TIMER0 3 (3)
61    CortexM33::GENERIC_ISR, // TIMER1 0 (4)
62    CortexM33::GENERIC_ISR, // TIMER1 1 (5)
63    CortexM33::GENERIC_ISR, // TIMER1 2 (6)
64    CortexM33::GENERIC_ISR, // TIMER1 3 (7)
65    CortexM33::GENERIC_ISR, // PWM_IRQ_WRAP 0 (8)
66    CortexM33::GENERIC_ISR, // PWM_IRQ_WRAP 1 (9)
67    CortexM33::GENERIC_ISR, // DMA 0 (10)
68    CortexM33::GENERIC_ISR, // DMA 1 (11)
69    CortexM33::GENERIC_ISR, // DMA 2 (12)
70    CortexM33::GENERIC_ISR, // DMA 3 (13)
71    CortexM33::GENERIC_ISR, // USB (14)
72    CortexM33::GENERIC_ISR, // PIO0 0 (15)
73    CortexM33::GENERIC_ISR, // PIO0 1 (16)
74    CortexM33::GENERIC_ISR, // PIO1 0 (17)
75    CortexM33::GENERIC_ISR, // PIO1 1 (18)
76    CortexM33::GENERIC_ISR, // PIO2 0 (19)
77    CortexM33::GENERIC_ISR, // PIO2 1 (20)
78    CortexM33::GENERIC_ISR, // IO_IRQ_BANK 0 (21)
79    CortexM33::GENERIC_ISR, // IO_IRQ_BANK 0 NS (22)
80    CortexM33::GENERIC_ISR, // IO_IRQ_QSPI (23)
81    CortexM33::GENERIC_ISR, // IO_IRQ_QSPI_NS (24)
82    CortexM33::GENERIC_ISR, // SIO_IRQ_FIFO (25)
83    CortexM33::GENERIC_ISR, // SIO_IRQ_BELL (26)
84    CortexM33::GENERIC_ISR, // SIO_IRQ_FIFO_NS (27)
85    CortexM33::GENERIC_ISR, // SIO_IRQ_BELL_NS (28)
86    CortexM33::GENERIC_ISR, // SIO_IRQ_MTIMECMP (29)
87    CortexM33::GENERIC_ISR, // CLOCKS (30)
88    CortexM33::GENERIC_ISR, // SPI 0 (31)
89    CortexM33::GENERIC_ISR, // SPI 1 (32)
90    CortexM33::GENERIC_ISR, // UART 0 (33)
91    CortexM33::GENERIC_ISR, // UART 1 (34)
92    CortexM33::GENERIC_ISR, // ADC_IRQ_FIFO (35)
93    CortexM33::GENERIC_ISR, // I2C 0 (36)
94    CortexM33::GENERIC_ISR, // I2C 1 (37)
95    CortexM33::GENERIC_ISR, // OTP (38)
96    CortexM33::GENERIC_ISR, // TRNG (39)
97    CortexM33::GENERIC_ISR, // PROC 0 (40)
98    CortexM33::GENERIC_ISR, // PROC 1 (41)
99    CortexM33::GENERIC_ISR, // PLL_SYS (42)
100    CortexM33::GENERIC_ISR, // PLL_USB (43)
101    CortexM33::GENERIC_ISR, // POWMAN_IRQ_POW (44)
102    CortexM33::GENERIC_ISR, // POWMAN_IRQ_TIMER (45)
103    unhandled_interrupt,    // (46)
104    unhandled_interrupt,    // (47)
105    unhandled_interrupt,    // (48)
106    unhandled_interrupt,    // (49)
107    unhandled_interrupt,    // (50)
108    unhandled_interrupt,    // (51)
109];
110
111extern "C" {
112    static mut _szero: usize;
113    static mut _ezero: usize;
114    static mut _etext: usize;
115    static mut _srelocate: usize;
116    static mut _erelocate: usize;
117}
118
119pub unsafe fn init() {
120    cortexm33::nvic::disable_all();
121    cortexm33::nvic::clear_all_pending();
122    let sio = gpio::SIO::new();
123    let processor = sio.get_processor();
124    match processor {
125        chip::Processor::Processor0 => {}
126        _ => panic!(
127            "Kernel should run only using processor 0 (now processor {})",
128            processor as u8
129        ),
130    }
131}
rp2350/lib.rs

rp2350/
lib.rs
