Expand description
Direct Memory Access (DMA) channels and multiplexer
§DMAMUX Channel Configuration Options
| ENBL | TRIG | A_ON | Function | Mode |
|---|---|---|---|---|
| 0 | X | X | DMA channel is disabled | Disabled Mode |
| 1 | 0 | 0 | DMA channel is enabled with no triggering (transparent) | Normal Mode |
| 1 | 1 | 0 | DMA channel is enabled with triggering | Periodic Trigger Mode |
| 1 | 0 | 1 | DMA channel is always enabled | Always On Mode |
| 1 | 1 | 1 | DMA channel is always enabled with triggering | Always On Trigger Mode |
Implementation assumptions:
- No minor loop mapping, assuming we don’t need to change addresses on minor loop runs.
- The driver exposes 32 DMA channels. This applies for nearly all i.MX RT 10xx chips, except for the 1011. Accessing any DMA channel beyond 15 will index into reserved memory.
When assigning DMA channels to peripherals, consider:
- How you could use channels that are 16 channel IDs apart, and complete DMA transfers with signaling from one DMA interrupt, instead of two separate interrupts.
- The first four DMA channels can be periodically scheduled from the four periodic interrupt timer (PIT) channels. Consider reserving those first four channels if you need to regularly schedule DMA transfers without CPU intervention.
- Channel priorities may come into play when preferring DMA channels. See the reference manual for more information on channel priorities, and how the DMA controller use priorities for scheduling.
Structs§
- The DMA peripheral exposes DMA channels.
- A DMA channel.
Enums§
- DMA hardware sources.
Traits§
- A type that responds to DMA completion events
- Describes a type that can be transferred via DMA.
Type Aliases§
- Indicates success or failure when executing a DMA transfer