earlgrey
0.2.3-dev
In earlgrey::
registers::
top_
earlgrey
Enums
AlertId
AlertPeripheral
DirectPads
GateableClocks
HintableClocks
MuxedPads
PinmuxInsel
PinmuxMioOut
PinmuxOutsel
PinmuxPeripheralIn
PlicIrqId
PlicPeripheral
PlicTarget
PowerManagerResetRequests
PowerManagerWakeUps
ResetManagerSwResets
Constants
ADC_CTRL_AON_BASE_ADDR
ADC_CTRL_AON_SIZE_BYTES
AES_BASE_ADDR
AES_SIZE_BYTES
ALERT_FOR_PERIPHERAL
ALERT_HANDLER_BASE_ADDR
ALERT_HANDLER_SIZE_BYTES
AON_TIMER_AON_BASE_ADDR
AON_TIMER_AON_SIZE_BYTES
AST_BASE_ADDR
AST_SIZE_BYTES
CLKMGR_AON_BASE_ADDR
CLKMGR_AON_SIZE_BYTES
CSRNG_BASE_ADDR
CSRNG_SIZE_BYTES
EDN0_BASE_ADDR
EDN0_SIZE_BYTES
EDN1_BASE_ADDR
EDN1_SIZE_BYTES
EFLASH_BASE_ADDR
EFLASH_SIZE_BYTES
ENTROPY_SRC_BASE_ADDR
ENTROPY_SRC_SIZE_BYTES
FLASH_CTRL_CORE_BASE_ADDR
FLASH_CTRL_CORE_SIZE_BYTES
FLASH_CTRL_MEM_BASE_ADDR
FLASH_CTRL_MEM_SIZE_BYTES
FLASH_CTRL_PRIM_BASE_ADDR
FLASH_CTRL_PRIM_SIZE_BYTES
GPIO_BASE_ADDR
GPIO_SIZE_BYTES
HMAC_BASE_ADDR
HMAC_SIZE_BYTES
I2C0_BASE_ADDR
I2C0_SIZE_BYTES
I2C1_BASE_ADDR
I2C1_SIZE_BYTES
I2C2_BASE_ADDR
I2C2_SIZE_BYTES
KEYMGR_BASE_ADDR
KEYMGR_SIZE_BYTES
KMAC_BASE_ADDR
KMAC_SIZE_BYTES
LC_CTRL_BASE_ADDR
LC_CTRL_SIZE_BYTES
MMIO_BASE_ADDR
MMIO_SIZE_BYTES
NUM_DIO_PADS
NUM_MIO_PADS
OTBN_BASE_ADDR
OTBN_SIZE_BYTES
OTP_CTRL_CORE_BASE_ADDR
OTP_CTRL_CORE_SIZE_BYTES
OTP_CTRL_PRIM_BASE_ADDR
OTP_CTRL_PRIM_SIZE_BYTES
PATTGEN_BASE_ADDR
PATTGEN_SIZE_BYTES
PINMUX_AON_BASE_ADDR
PINMUX_AON_SIZE_BYTES
PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET
PINMUX_PERIPH_OUTSEL_IDX_OFFSET
PLIC_INTERRUPT_FOR_PERIPHERAL
PWM_AON_BASE_ADDR
PWM_AON_SIZE_BYTES
PWRMGR_AON_BASE_ADDR
PWRMGR_AON_SIZE_BYTES
RAM_MAIN_BASE_ADDR
RAM_MAIN_SIZE_BYTES
RAM_RET_AON_BASE_ADDR
RAM_RET_AON_SIZE_BYTES
ROM_BASE_ADDR
ROM_CTRL_REGS_BASE_ADDR
ROM_CTRL_REGS_SIZE_BYTES
ROM_CTRL_ROM_BASE_ADDR
ROM_CTRL_ROM_SIZE_BYTES
ROM_SIZE_BYTES
RSTMGR_AON_BASE_ADDR
RSTMGR_AON_SIZE_BYTES
RV_CORE_IBEX_CFG_BASE_ADDR
RV_CORE_IBEX_CFG_SIZE_BYTES
RV_DM_MEM_BASE_ADDR
RV_DM_MEM_SIZE_BYTES
RV_DM_REGS_BASE_ADDR
RV_DM_REGS_SIZE_BYTES
RV_PLIC_BASE_ADDR
RV_PLIC_SIZE_BYTES
RV_TIMER_BASE_ADDR
RV_TIMER_SIZE_BYTES
SENSOR_CTRL_BASE_ADDR
SENSOR_CTRL_SIZE_BYTES
SPI_DEVICE_BASE_ADDR
SPI_DEVICE_SIZE_BYTES
SPI_HOST0_BASE_ADDR
SPI_HOST0_SIZE_BYTES
SPI_HOST1_BASE_ADDR
SPI_HOST1_SIZE_BYTES
SRAM_CTRL_MAIN_RAM_BASE_ADDR
SRAM_CTRL_MAIN_RAM_SIZE_BYTES
SRAM_CTRL_MAIN_REGS_BASE_ADDR
SRAM_CTRL_MAIN_REGS_SIZE_BYTES
SRAM_CTRL_RET_AON_RAM_BASE_ADDR
SRAM_CTRL_RET_AON_RAM_SIZE_BYTES
SRAM_CTRL_RET_AON_REGS_BASE_ADDR
SRAM_CTRL_RET_AON_REGS_SIZE_BYTES
SYSRST_CTRL_AON_BASE_ADDR
SYSRST_CTRL_AON_SIZE_BYTES
UART0_BASE_ADDR
UART0_SIZE_BYTES
UART1_BASE_ADDR
UART1_SIZE_BYTES
UART2_BASE_ADDR
UART2_SIZE_BYTES
UART3_BASE_ADDR
UART3_SIZE_BYTES
USBDEV_BASE_ADDR
USBDEV_SIZE_BYTES
earlgrey
::
registers
::
top_earlgrey
Constant
EFLASH_BASE_ADDR
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Summary
Source
pub const EFLASH_BASE_ADDR:
usize
= 0x20000000;
Expand description
Memory base address for eflash in top earlgrey.