Module cortexm7::nvic

Cortex-M NVIC

Most NVIC configuration is in the NVIC registers: https://developer.arm.com/docs/100165/0201/nested-vectored-interrupt-controller/nvic-programmers-model/table-of-nvic-registers

Also part of the NVIC conceptually is the ICTR, which in older versions of the ARM ARM was listed in the “Summary of system control and ID registers not in the SCB” and newer ARM ARMs just file it in its own little private sub-section with the NVIC documentation. Seems a configuration register without a home, so we include it in the NVIC files as it’s conceptually here. https://developer.arm.com/docs/ddi0337/latest/nested-vectored-interrupt-controller/nvic-programmers-model/interrupt-controller-type-register-ictr

Structs

• Nvic
  An opaque wrapper for a single NVIC interrupt.

Functions

• clear_all_pending^⚠
  Clear all pending interrupts
• disable_all^⚠
  Disable all interrupts
• enable_all^⚠
  Enable all interrupts
• has_pending^⚠
• has_pending_with_mask^⚠
  Returns whether there are any pending interrupt bits set while ignoring the indices that correspond to the bits set in mask
• next_pending^⚠
  Get the index (0-240) the lowest number pending interrupt, or None if none are pending.
• next_pending_with_mask^⚠
  Get the index (0-240) the lowest number pending interrupt while ignoring the interrupts that correspond to the bits set in mask, or None if none are pending.