Expand description
Implementation of the memory protection unit for the Cortex-M0+, Cortex-M3, Cortex-M4, and Cortex-M7
Structs§
- Per-process struct storing MPU configuration for cortex-m MPUs.
- Struct storing configuration for a Cortex-M MPU region.
- State related to the real physical MPU.
- MPU Registers for the Cortex-M3, Cortex-M4 and Cortex-M7 families Described in section 4.5 of http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf