Module bus

Abstraction Interface for several busses. Useful for devices that support multiple protocols

Usage

I2C example

let bus = components::bus::I2CMasterBusComponent::new(i2c_mux, address)
    .finalize(components::spi_bus_component_helper!());

SPI example

let bus =
    components::bus::SpiMasterBusComponent::new().finalize(components::spi_bus_component_helper!(
        // spi type
        nrf52840::spi::SPIM,
        // chip select
        &nrf52840::gpio::PORT[GPIO_D4],
         // spi mux
        spi_mux
    ));

Structs

Bus8080Bus

BusAddr8

Each BusAddr struct represents a specific data width and endianness. 8 bit Bus Address

BusAddr16BE

16 bit Big Endian Bus Address

BusAddr16LE

16 bit Little Endian Bus Address

BusAddr32BE

32 bit Big Endian Bus Address

BusAddr32LE

32 bit Little Endian Bus Address

BusAddr64BE

64 bit Big Endian Bus Address

BusAddr64LE

64 bit Little Endian Bus Address

I2CMasterBus

SpiMasterBus

Enums

DataWidth

The DataWidth enum and associated BusAddr structs define the width of the data transmitted over a bus.

Traits

Bus

BusAddr

The BusAddr trait is implemented for each BusAddr struct. It provides information about the data width and a way to access the underlying byte representation.

Client